Minimizing Latency for Financial Data
Step AT used their reconfigurable module for CompactRIO to measure the transfert time of financial information for low trading applications.
Step AT specializes in the design of products for embedded and real-time applications, including customization of the CompactRIO platform through additional modules to add functionality to the FPGA target. It is in this framework that the company Wall Street FPGA, based in New York and speaker in the field of finance for a US financial information firm, appealed to our services.
The same start time for everyone
Rating of the stock data is disseminated by specialized agencies and whose ranking is performed on a regular basis to allow subscribers to choose the most efficient. One of these agencies entrusted to Wall Street FPGA care to design a monitoring system to search for a way to speed up the time of dissemination of these data.
Opening of markets, these "switches" in each agency close for them to disseminate the values of rating to allow speculation. These data are encapsulated in UDP multicast packets spaced between them of 200 microseconds. Every microsecond in the pipes of the internal network agencies delay their dissemination; it is for this that knowledge of the time of the spread of valuable data is essential and this through the use of a source of accurate as a NTP (Network Time Protocol) server time.
The CompactRIO platform enables with its bottom of basket FPGA to develop applications by minimizing the latency in the acquisition and processing of data. In this application, the Wall Street FPGA company wanted therefore acquires and process the data only from the FPGA without resorting to the real time controller. The main problem lies in the fact that the UDP multicast drivers and the NTP client are available on the controller and thus unworkable in this application.
1 CompactRIO module tailored to meet the need
Wall Street FPGA has contacted us to find a solution that able to process packets UDP multicast and NTP directly from the FPGA through a C Series module designed for the requirement. We had developed since little module OCRI based on an ARM processor offering a degree of customization large enough through the programming of the heart of using LabVIEW Embedded module for ARM and it is of course that we have proposed to meet the need (UDP multicast-client NTP) with 2 modules based on the same hardware architecture (base ARM processor) but with a different firmware.
The first module was loaded to recover packets corresponding to stock and to transmit them to the bottom of basket FPGA via an SPI bus. The second module provides a source of clock accurate enough to allow the timestamp of the UDP packets.
Very identified requirements
The final client wanted to learn the UDP packets, and date them with less than 100 microseconds accuracy. The only way to achieve this was to synchronize the internal clock of the ARM microprocessor at clock accuracy from a time server NTP. The principle of synchronization on an Ethernet network is to estimate a delay between the master clock (the server from an atomic clock or GPS) and one slave (clock of the CompactRIO module) through exchanges of time markers to move the slave clock. The aim being to date precisely the packages, the module receiving UDP triggers a digital line directly sent to the NTP module to minimize the latency on the determination of the absolute time of receipt of the UDP frame.
A development simplified
Through the joint use of LabVIEW FPGA and LabVIEW Embedded for ARM, we were able to develop a solution for Wall Street FPGA and allow them to propose this system of monitoring within a reasonable time despite the distance and the impossibility for us to really debug the application on site.
If in the future, the solution is validated by the client, we can provide new module Wall Street FPGA in order to equip new agency in the United States.